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PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
Rev. 05 -- 2 September 2009 Product data sheet
1. Product profile
1.1 General description
PNP Resistor-Equipped Transistors (RET).
Table 1. Product overview Package NXP PDTA113EE PDTA113EK PDTA113EM PDTA113ES[1] PDTA113ET PDTA113EU
[1]
Type number
JEITA SC-75 SC-59A SC-101 SC-43A SC-70
JEDEC TO-236 TO-92 TO-236AB -
NPN complement PDTC113EE PDTC113EK PDTC113EM PDTC113ES PDTC113ET PDTC113EU
SOT416 SOT346 SOT883 SOT54 (TO-92) SOT23 SOT323
Also available in SOT54A and SOT54 variant packages (see Section 2)
1.2 Features
I Built-in bias resistors I Simplifies circuit design I Reduces component count I Reduces pick and place costs
1.3 Applications
I General purpose switching and amplification I Inverter and interface circuits I Circuit drivers
1.4 Quick reference data
Table 2. Symbol VCEO IO R1 R2/R1 Quick reference data Parameter collector-emitter voltage output current (DC) bias resistor 1 (input) bias resistor ratio Conditions open base Min 0.7 0.8 Typ 1 1 Max -50 -100 1.3 1.2 Unit V mA k
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
2. Pinning information
Table 3. Pin SOT54 1 2 3 input (base) output (collector) GND (emitter)
1 2 3
001aab347 006aaa148
Pinning Description Simplified outline Symbol
2 R1 1 R2 3
SOT54A 1 2 3 input (base) output (collector) GND (emitter)
1 2 3
001aab348 006aaa148
2 R1 1 R2 3
SOT54 variant 1 2 3 input (base) output (collector) GND (emitter)
1 2 3
001aab447 006aaa148
2 R1 1 R2 3
SOT23, SOT323, SOT346, SOT416 1 2 3 input (base) GND (emitter) output (collector)
1 2
006aaa144 sym003
3
R1
3 1
R2
2
SOT883 1 2 3 input (base) GND (emitter) output (collector)
1 3 2 Transparent top view 1
R2 R1
3
2
sym003
PDTA113E_SER_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
2 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
3. Ordering information
Table 4. Ordering information Package Name PDTA113EE PDTA113EK PDTA113EM PDTA113ES[1] PDTA113ET PDTA113EU
[1]
Type number
Description plastic surface mounted package; 3 leads plastic surface mounted package; 3 leads leadless ultra small plastic package; 3 solder lands; body 1.0 x 0.6 x 0.5 mm
Version SOT416 SOT346 SOT883
SC-75 SC-59A SC-101 SC-43A SC-70
plastic single-ended leaded (through hole) package; SOT54 3 leads plastic surface mounted package; 3 leads plastic surface mounted package; 3 leads SOT23 SOT323
Also available in SOT54A and SOT54 variant packages (see Section 2 and Section 9).
4. Marking
Table 5. Marking codes Marking code[1] 16 17 G4 TA113E *15 *14 Type number PDTA113EE PDTA113EK PDTA113EM PDTA113ES PDTA113ET PDTA113EU
[1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China
PDTA113E_SER_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
3 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
5. Limiting values
Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCBO VCEO VEBO VI Parameter collector-base voltage collector-emitter voltage emitter-base voltage input voltage positive negative IO ICM Ptot output current (DC) peak collector current total power dissipation SOT416 SOT346 SOT883 SOT54 SOT23 SOT323 Tstg Tj Tamb
[1] [2] [3]
Conditions open emitter open base open collector
Min -
Max -50 -50 -10 +10 -10 -100 -100 150 250 250 500 250 200 +150 150 +150
Unit V V V V V mA mA mW mW mW mW mW mW C C C
Tamb 25 C
[1] [1] [2][3] [1] [1] [1]
-65 -65
storage temperature junction temperature ambient temperature
Refer to standard mounting conditions Reflow soldering is the only recommended soldering method. Refer to SOT883 standard mounting conditions; FR4 printed-circuit board with 60 m copper strip line.
6. Thermal characteristics
Table 7. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient SOT416 SOT346 SOT883 SOT54 SOT23 SOT323
[1] [2] [3] Refer to standard mounting conditions. Reflow soldering is the only recommended soldering method. Refer to SOT883 standard mounting conditions; FR4 printed-circuit board with 60 m copper strip line.
Conditions in free air
[1] [1] [2][3] [1] [1] [1]
Min
Typ
Max
Unit
-
-
833 500 500 250 500 625
K/W K/W K/W K/W K/W K/W
PDTA113E_SER_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
4 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
7. Characteristics
Table 8. Characteristics Tamb = 25 C unless otherwise specified Symbol ICBO ICEO Parameter collector-base cut-off current collector-emitter cut-off current emitter-base cut-off current DC current gain collector-emitter saturation voltage off-state input voltage on-state input voltage bias resistor 1 (input) bias resistor ratio collector capacitance VCB = -10 V; IE = ie = 0 A; f = 1 MHz Conditions VCB = -50 V; IE = 0 A VCE = -30 V; IB = 0 A VCE = -30 V; IB = 0 A; Tj = 150 C VEB = -5 V; IC = 0 A VCE = -5 V; IC = -40 mA IC = -30 mA; IB = -1.5 mA VCE = -5 V; IC = -100 A VCE = -300 mV; IC = -20 mA Min 30 -2 0.7 0.8 Typ -1.3 -1.7 1 1 Max -100 -1 -50 -4 -150 -0.5 1.3 1.2 2 pF mV V V k Unit nA A A mA
IEBO hFE VCEsat VI(off) VI(on) R1 R2/R1 Cc
PDTA113E_SER_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
5 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
102 hFE
006aaa115
(2) (1) (3)
-1
006aaa116
VCEsat (V) 10 -10-1
(1) (2) (3)
1
10-1 -10-1
-1
-10 I C (mA)
-102
-10-2 -10 I C (mA)
-102
VCE = -5 V (1) Tamb = 100 C (2) Tamb = 25 C (3) Tamb = -40 C
IC/IB = 20 (1) Tamb = 100 C (2) Tamb = 25 C (3) Tamb = -40 C
Fig 1.
DC current gain as a function of collector current; typical values
006aaa117
Fig 2.
Collector-emitter saturation voltage as a function of collector current; typical values
006aaa118
-10
-10
VI(on) (V)
(1) (2) (3)
VI(off) (V)
(1) (2) (3)
-1
-1
-10-1 -10-1
-1
-10 I C (mA)
-102
-10-1 -10-1
-1 I C (mA)
-10
VCE = -0.3 V (1) Tamb = -40 C (2) Tamb = 25 C (3) Tamb = 100 C
VCE = -5 V (1) Tamb = -40 C (2) Tamb = 25 C (3) Tamb = 100 C
Fig 3.
On-state input voltage as a function of collector current; typical values
Fig 4.
Off-state input voltage as a function of collector current; typical values
PDTA113E_SER_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
6 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
8. Package outline
Plastic surface-mounted package; 3 leads SOT416
D
B
E
A
X
vMA
HE
3
Q
A
1
e1 e bp
2
wM B
A1 c
Lp detail X
0
0.5 scale
1 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 0.95 0.60 A1 max 0.1 bp 0.30 0.15 c 0.25 0.10 D 1.8 1.4 E 0.9 0.7 e 1 e1 0.5 HE 1.75 1.45 Lp 0.45 0.15 Q 0.23 0.13 v 0.2 w 0.2
OUTLINE VERSION SOT416
REFERENCES IEC JEDEC JEITA SC-75
EUROPEAN PROJECTION
ISSUE DATE 04-11-04 06-03-16
Fig 5.
Package outline SOT416 (SC-75)
(c) NXP B.V. 2009. All rights reserved.
PDTA113E_SER_5
Product data sheet
Rev. 05 -- 2 September 2009
7 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
Plastic surface-mounted package; 3 leads
SOT346
E D B
A X
HE
vMA
3
Q
A A1
1
e1 e bp
2
wMB detail X Lp
c
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.3 1.0 A1 0.1 0.013 bp 0.50 0.35 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 1.9 e1 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2
OUTLINE VERSION SOT346
REFERENCES IEC JEDEC TO-236 JEITA SC-59A
EUROPEAN PROJECTION
ISSUE DATE 04-11-11 06-03-16
Fig 6.
Package outline SOT346 (SC-59A/TO-236)
(c) NXP B.V. 2009. All rights reserved.
PDTA113E_SER_5
Product data sheet
Rev. 05 -- 2 September 2009
8 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
Leadless ultra small plastic package; 3 solder lands; body 1.0 x 0.6 x 0.5 mm
SOT883
L 2 b e
L1
3
b1
1
e1
A A1
E
D
0
0.5 scale
1 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A (1) 0.50 0.46 A1 max. 0.03 b 0.20 0.12 b1 0.55 0.47 D 0.62 0.55 E 1.02 0.95 e 0.35 e1 0.65 L 0.30 0.22 L1 0.30 0.22
Note 1. Including plating thickness OUTLINE VERSION SOT883 REFERENCES IEC JEDEC JEITA SC-101 EUROPEAN PROJECTION ISSUE DATE 03-02-05 03-04-03
Fig 7.
Package outline SOT883 (SC-101)
(c) NXP B.V. 2009. All rights reserved.
PDTA113E_SER_5
Product data sheet
Rev. 05 -- 2 September 2009
9 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
Plastic single-ended leaded (through hole) package; 3 leads
SOT54
c
E d A L b
1
D
2
e1 e
3
b1
L1
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 5.2 5.0 b 0.48 0.40 b1 0.66 0.55 c 0.45 0.38 D 4.8 4.4 d 1.7 1.4 E 4.2 3.6 e 2.54 e1 1.27 L 14.5 12.7 L1(1)
max.
2.5
Note 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 REFERENCES IEC JEDEC TO-92 JEITA SC-43A EUROPEAN PROJECTION ISSUE DATE 04-06-28 04-11-16
Fig 8.
Package outline SOT54 (SC-43A/TO-92)
(c) NXP B.V. 2009. All rights reserved.
PDTA113E_SER_5
Product data sheet
Rev. 05 -- 2 September 2009
10 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
Plastic single-ended leaded (through hole) package; 3 leads (wide pitch)
SOT54A
c
E d
A L2
L b
1
D
e1 e
2 3
b1
L1
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 5.2 5.0 b 0.48 0.40 b1 0.66 0.55 c 0.45 0.38 D 4.8 4.4 d 1.7 1.4 E 4.2 3.6 e 5.08 e1 2.54 L 14.5 12.7 L1(1)
max.
L2 3 2
3
Note 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54A REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 97-05-13 04-06-28
Fig 9.
Package outline SOT54A
(c) NXP B.V. 2009. All rights reserved.
PDTA113E_SER_5
Product data sheet
Rev. 05 -- 2 September 2009
11 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
Plastic single-ended leaded (through hole) package; 3 leads (on-circle)
SOT54 variant
c
e1
L2
E d A L b
1 2
D e1 e
3
b1
L1
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 5.2 5.0 b 0.48 0.40 b1 0.66 0.55 c 0.45 0.38 D 4.8 4.4 d 1.7 1.4 E 4.2 3.6 e 2.54 e1 1.27 L 14.5 12.7 L1(1) max 2.5 L2 max 2.5
Note 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 variant REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-06-28 05-01-10
Fig 10. Package outline SOT54 variant
PDTA113E_SER_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
12 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
Plastic surface-mounted package; 3 leads
SOT23
D
B
E
A
X
HE
vMA
3
Q A A1
1
e1 e bp
2
wMB detail X Lp
c
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max. 0.1 bp 0.48 0.38 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 0.95 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1
OUTLINE VERSION SOT23
REFERENCES IEC JEDEC TO-236AB JEITA
EUROPEAN PROJECTION
ISSUE DATE 04-11-04 06-03-16
Fig 11. Package outline SOT23 (TO-236AB)
PDTA113E_SER_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
13 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
Plastic surface-mounted package; 3 leads
SOT323
D
B
E
A
X
y
HE
vMA
3
Q
A
A1 c
1
e1 e bp
2
wM B Lp detail X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.4 0.3 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.23 0.13 v 0.2 w 0.2
OUTLINE VERSION SOT323
REFERENCES IEC JEDEC JEITA SC-70
EUROPEAN PROJECTION
ISSUE DATE 04-11-04 06-03-16
Fig 12. Package outline SOT323 (SC-70)
PDTA113E_SER_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
14 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
9. Packing information
Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code. [1] Type number PDTA113EE PDTA113EK PDTA113EM PDTA113ES Package SOT416 SOT346 SOT883 SOT54 SOT54A SOT54A SOT54 variant PDTA113ET PDTA113EU
[1]
Description 4 mm pitch, 8 mm tape and reel 4 mm pitch, 8 mm tape and reel 2 mm pitch, 8 mm tape and reel bulk, straight leads tape and reel, wide pitch tape ammopack, wide patch bulk, delta pinning 4 mm pitch, 8 mm tape and reel 4 mm pitch, 8 mm tape and reel
Packing quantity 3000 -115 -115 -215 -115 5000 -412 -112 10000 -135 -135 -315 -116 -126 -235 -135
SOT23 SOT323
For further information and the availability of packing methods, see Section 12.
PDTA113E_SER_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
15 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
10. Revision history
Table 10. Revision history Release date 20090902 Data sheet status Product data sheet Change notice Supersedes PDTA113E_SER_4 Document ID PDTA113E_SER_5 Modifications:
* * * * *
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content. Figure 5 "Package outline SOT416 (SC-75)" updated Figure 6 "Package outline SOT346 (SC-59A/TO-236)" updated Figure 11 "Package outline SOT23 (TO-236AB)" updated Figure 12 "Package outline SOT323 (SC-70)" updated Product data sheet Objective data sheet Objective data sheet Objective data sheet PDTA113ET_3 PDTA113ET_2 PDTA113ET_1 -
PDTA113E_SER_4 PDTA113ET_3 PDTA113ET_2 PDTA113ET_1
20050405 20040720 20040415 20040316
PDTA113E_SER_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
16 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
11. Legal information
11.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
11.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
11.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
11.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
12. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PDTA113E_SER_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 2 September 2009
17 of 18
NXP Semiconductors
PDTA113E series
PNP resistor-equipped transistors; R1 = 1 k, R2 = 1 k
13. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 11.1 11.2 11.3 11.4 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Packing information. . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 September 2009 Document identifier: PDTA113E_SER_5

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